Education

Under Construction

Updated: Wednesday February 27, 2008

     

Home
About Me
Education
Contact

 

 
RESUME

 

   UT Graduate Cousework

  •   EE382M (Topic 1) - VLSI Testing
  •   EE382M (Topic 7) - VLSI I
  •   EE382M (Topic 8) - VLSI II
  •   EE383P (Topic 6) - Optoelectronic Devices
  •   EE390C - Statistical Methods in Engineering and Quality Assurance
  •   EE396K (Topic 26) - Microelectromechanical Systems
  •   EE396K (Topic 8) - VLSI Fabrication Techniques
  •   EE396K (Topic 25) - Organic/Polymer Semiconductor Devices
  •   EE396K (Topic 21) - Submicron Device Physics and Technologies

 

   UT Undergraduate Cousework

  •   EE339 - Solid-State Electronic Devices
  •   EE379K - Solar Conversion Devices
  •   EE438 - Electronic Circuits I

 

 

 

  EE339 - Solid-State Electronic Devices

  • Intro / Semiconductors - crystal growth

  • Quantum Concepts

  • Energy bands in solids; Effective mass approximation; Electrons and holes carrier concentrations

  • Drift currents; Mobility / Hall effect

  • Carrier lifetime and photoconductivity

  • Diffusions: P-N junctions

  • Metal-semiconductor contacts; Field-effect transistors

  • FET's; MIS and MOS versions

  • Bipolar junction transistors (BJT's)

  • Optoelectronic Devices (LED's, lasers, etc...)

 

 

  EE379K - Solar Conversion Devices

  • Principles of photovoltaics

  • Electrons and holes in semiconductors

  • Generation and recombination

  • Junctions; Analysis of p-n junctions

  • Monocrystalline solar cells

  • Silicon solar cell design and optimization

  • Thin film solar cells

  • Managing light; Strategies for higher efficiency

  • Solar cells based on organics and nanocrystals

  • Non-photovoltaic approaches to solar energy conversion

 

 

  EE438 - Electronic Circuits I

  • Amplifiers, Circuit models for amplifiers, Frequency response of amplifiers

  • Physical operation of diodes, The ideal diode, Forward bias characteristics, Reverse bias operation (Zener diodes), Rectifiers circuits, Limiting and clamping circuits

  • MOSFETs: Device structure and physical operation, Current-voltage characteristics, MOSFET circuits at DC, Biasing in MOS amplifier circuits, Small signal operation and models, Single stage amplifiers, Internal capacitances and high-frequency model, Frequency response of the CS amplifier

  • BJTs:  Device structure and physical operation, Current-voltage characteristics, BJT circuits at DC, Biasing in BJT amplifier circuits, Small signal operation and models, Single stage amplifiers, Internal capacitances and high-frequency model, Frequency response of the common emitter amplifier

  • Single-Stage Integrated Circuit Amplifiers: Current sources, Current mirrors, Current steering circuits, High frequency response, CS and CE amplifiers, CG and CB amplifiers, Cascode amplifiers, Source and emitter followers

  • Differential and Multistage Amplifiers: The MOS differential pair, Small-signal operation of MOS differential pair, BJT differential pair, Differential amplifier with active load, Frequency response of differential amplifier, Multistage CMOS op amp and bipolar op amp

Lab Section: covers generation and acquisition of test signals; current, voltage, and impedance measurements; transfer function measurement; and spectrum measurements and analysis.

 

 

  EE382M (Topic 1) - VLSI Testing

  • Fault modeling

  • Boolean testing

  • Fault simulation

  • Test pattern generation

  • Sequential circuit testing

  • Design for testability

  • Built in Self Test (BIST)

  • Test compression

  • Memory test

  • Delay test

  • Logic Diagnosis

  • Mixed-signal testing and other test methods

Class Projects:

Lab 1
Write code, in C, to implement a 3-valued fault simulator. The fault simulator will be run in different circuits; fault coverage and speed will be graded.
 

Lab 2
Design the BIST hardware, in Verilog, for a circuit-under-test (CUT) that has a scan chain composed of Muxed-D scan cells. The BIST hardware needs to apply 2000 pseudo-random scan patterns to the CUT and compact the response.

 

 

  EE382M (Topic 7) - VLSI I

  • CMOS transistors, CMOS fabrication and layout, CMOS logic

  • MOS transistor theory

  • DC and transient gate characteristics

  • Logical effort

  • Combinational circuits

  • Design of adders

  • Datapath

  • Interconnects in CMOS technology

  • Sequential elements, Design styles

  • Hardware description languages, Synthesis

  • Memories

  • Dynamic CMOS logic

  • Deep submicron issues

  • CAMs, ROMs, PLAs

  • Circuit pitfalls

  • Introduction to test

  • Packaging and I/O

  • Circuit optimization, Design for low power, Skew-tolerant design

  • Scaling and economics, evolution of microprocessor

Class Projects:

Lab 1
Part A - Design a 4-bit register. Generate schematics (Cadence), design circuit layout (Cadence), Layout extraction to obtain netlist (Cadence), circuit characterization (SPICE). Circuit size and functionary will be graded.
Part B - Investigate the design of a 32x32 memory and create a full simulation to test a memory array, and the memory read performance. Model RC delay for the memory cell, construct schematic for the worst delay path of the 32x32 (1K) memory array, connect memory array to decoder, implement memory deck to test memory array, and measure the worst case access time. Tools use include HSpice and Awaves.
 

Lab 2
Part A - Design a 16-bit adder following the complete VLSI design flow. Construct the adder design of your choice in Cadence Virtuoso Composer, test its functionality using Verilog XL, and test the circuit's critical path delay using Primetime. Functionality and speed will be graded.
Part B - Design a 16-bit arithmetic logic unit (ALU) incorporating the adder designed in part a. Circuit must perform the  specified logic, arithmetic, shifting, and conditioning operations correctly. Design schematic (Cadence), test functionality (Verilog-XL), determine critical path delay using static timing analysis software (Primetime), and generate the layout by using an automatic place and route tool (Silicon Ensemble). Functionality, speed, and APR layout size will be graded.

 

Lab 3
 

 

 

  EE382M (Topic 8) - VLSI II

  • Transistor and process technology

  • Early design planning (EDP): Front End and Back End

  • Flip-flop design

  • Timing analysis for EDP

  • Global clocking

  • Array design for EDP

  • Power delivery and management

  • DSM interconnect

  • Variable aware circuit design

  • Static and statistical timing analysis

  • Dynamic circuits

  • Array circuit design

  • Noise

  • I/O, ESD

  • Deep pipelined design

  • DFT, DFD, DFX

  • Arch design for low power, circuit design for low power

  • Asynchronous design

 

 

  EE383P (Topic 6) - Optoelectronic Devices

  • Review of basic physics: crystals, quantum, band structure, density of states, statistical mechanics

  • Heterostructures: band alignments, band diagrams, etc...

  • Strain: critical thickness, band structure changes (energy shifts, symmetries, etc...)

  • Crystal Growth: liquid phase epitaxy, molecular beam epitaxy, metalorganic chemical vapor deposition

  • Optical Processes: Fermi's Golden Rule, Einstein's A & B coefficients, absorption (3-D, 2-D, 1-D, 0-D), emission/gain, strain effects, refraction, parasitic losses

  • Semiconductor Diodes: Diodes (hetero- and homojunction), tunneling, meta/semiconductor interfaces

  • Light Emitting Diodes

  • Photodetectors: Photoconductors, avalanche photodiodes, MSM photodiodes, intersubband

  • Photovoltaics

  • Modulators: Electro-absorption and electro-optic, device geometries

  • Semiconductor Lasers: cavities and resonators, Rogrod analysis, rate equations, laser structures: edge-emitting, vertical-cavity, distributed feedback, quantum cascade, optical amplifiers

  • Terahertz Generation/Detection: Photomixers, Austin switches, Schottky detectors

 

 

  EE390C - Statistical Methods in Engineering and Quality Assurance

  • Probability properties and applications

  • Descriptive statistics and the Normal distribution

  • Proportion estimation and confidence intervals

  • Hypothesis testing

  • Chi-Squared distribution and variance tests

  • F distribution and variance tests

  • Individuals and MR charts, XBAR and S charts

  • XBAR and R charts, attribute charts

  • Pairwise t-tests, 1-way ANOVAs, 2-way ANOVAs

  • Multiple comparisons and response surface designs

  • Gauge studies and other applications

  • Experimental designs

 

 

  EE396K (Topic 26) - Microelectromechanical Systems

  • Intro to MEMS: actuators and sensor examples

  • Material properties: thermal; mechanical properties

  • Cantilever beams

  • Dynamic mechanical response

  • Force mechanisms: electrostatic, thermal

  • Basic materials: Silicon, impurities, defects

  • Thin film growth and deposition; Lithography; Etching

  • Bulk and RIE anisotropic etching; Deep RIE, CMP, plating, bonding, etc...

  • Strain and pressure sensors

  • Fabry-Perot pressure sensor

  • Design of F-P sensor for yield

  • Accelerometers

  • Bolometers for electromagnetic detection

  • Thermal losses in bolometers, fabrication, and performance

  • Chemical sensors: gas, vapor, and liquid phases

 

 

  EE396K (Topic 8) - VLSI Fabrication Techniques

  • CMOS process overview, Orientation effects, Impurities

  • Crystal growth, Impurities in CZ, Gettering, Oxigen in Si

  • Basic oxidation process, Oxidation kinetics, Doping effects

  • Mobile charge, Thin oxides

  • Diffusion, Fick's laws, Vacancy-Impurity interactions

  • Diffusion profiles, Boron and phosphorus diffusion

  • Ion implantation, Channeling, Implant damage, Annealing

  • Evaluation techniques of doped layers

  • Irvin curves, Hall effect,  Secondary ion mass spectroscopy (SIMS), C-V

  • Deposited thin films, Kinetic gas theory, Step coverage

  • Physical vapor deposition, Thermal evaporation, Sputtering, Chemical vapor deposition

  • Poly, Oxide, Nitride

  • Epitaxy, Autodoping, Pattern shift, Metallization

  • Electromigration, Contacts, Chemical mechanical polishing (CMP)

  • Lithography, Optical transfer, Masks, Masks aligners, Resists

  • Advanced lithography, Etching bias and selectivity

  • Plasma etching, Plasma processing

 

 

  EE396K (Topic 25) - Organic/Polymer Semiconductor Devices

  • Chemical structures, nomenclatures, crystal structures, electronic structure

  • Charge carriers and transport in crystalline organic semiconductors

  • Charge carriers in conjugated polymers, conducting polymers, solitons, polarons

  • Semiconducting polymers, charge carriers and transport in polycrystalline organic semiconductors

  • Charge transport in disordered materials

  • Optical properties of conjugated organics and polymers

  • Organic solar cells, polymer solar cells

  • Device physics and operation of bulk heterojunction cells

  • Organic light emitting diodes (OLEDS), white OLEDS and lighting

  • Color OLEDS and organic displays

  • Organic field effect transistors (OFET's), organic FET circuits

 

 

  EE396K (Topic 21) - Submicron Device Physics and Technologies

  • MOS Capacitors: Depletion approximation; General analysis

  • Applications of C-V and C-t plots

  • Interface traps and characterization techniques

  • Gate oxide and high-K dielectrics

  • MOSFET analysis: Simple model, general long-channel model

  • Subthreshold characteristics

  • Mobility model, velocity saturation; Temperature effects

  • Shorts channel effects: Drain-induced barrier lowering, punchthrough, ΔVt and ΔS, Vdsat model, short-channel MOS drain current model

  • Ion implanted devices/buried-channel devices

  • Hot electron effects

  • Lightly-doped drain MOSFET electric field model

  • Asymmetry effects (S/D non-overlap)

  • CMOS latchup; Gate-induced drain leakage current

  • Silicon-on-insulator (SOI) and 3-D devices

  • Poly-depletion and quantum mechanical effects

  • Bipolar transistors: Minority carrier concentration profile, current models, emitter injection efficiency/base transport factor

  • Current gain; Low-level injection effect; High-level injection effect; Early effect

  • Base storage time/base transit time

  • Kirk effect; Avalanche breakdown; punchthrough

 

 

Home | About Me | Education | Contact

 

Hit Counter
Visitor Counter

This site was last updated 02/27/08